1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly to a ferroelectric memory using a ferroelectric capacitor.
2. Description of the Related Art
The ferroelectric memory which is being researched nowadays is roughly classified into two systems. The one is a memory of a system in which the quantity of inverted charges of a ferroelectric capacitor is detected. This system, as seen from an equivalent circuit diagram shown in FIG. 5, includes a ferroelectric capacitor CF and a select transistor TSW.
The other is a memory of the system in which a change in the resistance of semiconductor due to spontaneous polarization of ferroelectric is detected. A representative system thereof is an MFSFET. This MFSFET is an FET in a MIS structure using ferroelectric for a gate insulating film.
The former ferroelectric memory can hold charges of two values of “0” and “1” in a single ferroelectric capacitor. For example, as understood from the hysteresis characteristic as shown in FIG. 6, where the storage information of “0” is written, with the voltage applied to the capacitor being minus (with a select transistor TSW being on, a minus potential is applied to a bit line BL and a plus potential is applied to a plate line PL) after having passed point d, the applied voltage is restored to zero. In this case, the polarized value results in a residual polarized point “a” so that the storage information of “0” can be written. On the other hand, where storage information of “1” is written, with the voltage applied to the capacitor being plus, after having passed point “b”, the applied voltage is restored to zero. In this case, the polarized value results in a residual polarized point c so that the storage information of “1” can be written.
The read of data can be executed in such a manner that the quantity of charges flowing into the bit line when the voltage is applied to the capacitor is detected.
The charges flowing from the ferroelectric capacitor into the bit line changes the potential on the bit line. The bit line has a parasitic bit line capacitance Cb generated because of the presence of the bit line itself When the select transistor is turned on to select the memory to be read, according to the information stored in each selected memory cell, the charge is outputted onto the bit line. The value obtained when this charge is divided by the entire capacitance of the bit line represents the potential on the bit line.
A difference between the bit line potentials is read in comparison with a predetermined reference potential.
Where a signal varying from (−) to (+) is applied to an ordinary capacitor CFE, as seen from FIG. 7A, residual dielectric polarization PSW is generated. On the other hand, where the signal varying from (+) to (−) is applied to the capacitor CFE, as seen from FIG. 7B, residual dielectric polarization −PSW is generated. Where a signal not varying while remaining (+) is applied to the capacitor CFE, as seen from FIG. 7C, residual dielectric polarization Pnon is generated. Where a signal not varying while remaining (−) is applied to the capacitor CFE, as seen from FIG. 7D, residual dielectric polarization −Pnon is generated.
The bit line potential based on the above residual dielectric polarization is read in comparison with the reference voltage so that the read of the stored data is executed.
Meanwhile, the ferroelectric capacitor has an “imprint characteristic” that the residual dielectric polarization generated after written is held. The quantity of held polarization is a value peculiar to the ferroelectric capacitor.
Now it is assumed that the signal corresponding to FIGS. 7A to 7D like the above case has been applied to the ferroelectric capacitor holding the imprinted polarization of −Pi. Where a signal varying from (−) to (+) is applied to the imprinted ferroelectric capacitor, as seen from FIG. 8A, residual dielectric polarization PSW−Pi is generated. On the other hand, where the signal varying from (+) to (−) is applied to the capacitor, as seen from FIG. 8B, residual dielectric polarization −(PSW+Pi) is generated. Where a signal not varying while remaining (+) is applied to the capacitor, as seen from FIG. 8C, residual dielectric polarization Pnon−P1 is generated. Where a signal not varying while remaining (−) is applied to the capacitor CFE, as seen from FIG. 8D, residual dielectric polarization −(Pnon+Pi) is generated.
Such an imprint characteristic becomes gradually remarkable with an increase in the number of times of write. This leads to failure of read because of a small margin in decision.